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Firmware Design

Software Flow Diagram

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Signal Generator (DAC)

The signal generator uses an R-2R ladder DAC connected to digital pins PB0 to PB7. Key features include:

  • 8-bit resolution, providing 256 steps.
  • A circular buffer for sine wave data, applied via interrupts.

Timer 1

Timer 1 is responsible for generating the sine wave through digital pins PB0 to PB7.
Timer Specifications:

  • Prescaler: 2
  • Interval: \(\frac{1}{frequency} \times \frac{1}{100}\)

Voltage & Current Measurement

Pin Description

VI - PA7 Pin

Measure VI
Voltage LOW
Current HIGH

GS - PA6 Pin

  • LOW:
  • HIGH: Gain is unity

ADC - PA0, PA1 Pins

  • PA0: Voltage and current measurement.
  • PA1: Automatic Factor Correction (AFC).

Measurement Mode Handling

  • Four possible modes are configured using the VI and GS pins.
  • To ensure accurate measurements, the mode is set with a time gap before measurement.
  • A total of 8 modes are cycled via Timer 2 interrupts.

Timer 2

Timer 2 toggles the VI measurement switch.
Timer Specifications: - Prescaler: 72000
- Interval: 250ms

Community Support: ADC Timer Implementation

ADC Configuration

The ADC operates in dual mode for PA0 (ADC0) and PA1 (ADC1). Key features include:

  • Timer 3 triggers ADC sampling via TRGO.
  • Direct Memory Access (DMA) is used to offload CPU load.
  • DMA overflow interrupts transfer ADC sample data to specific arrays.

Timer 3

Timer 3 triggers ADC measurements.
Timer Specifications: - Prescaler: 8
- Interval: \(\frac{1}{sampling frequency}\)

Display

The SSD1306 display (128x64 resolution) is connected via I2C using PA4 (SCL) and PA3 (SDA).

Implementation

Community Support: Display with Non-Standard I2C Pins

Miscellaneous Section

User Buttons

  • PB13: Hold
  • PB14: Serial/Parallel (S/P) mode
  • PB15: RCL mode